1. Field of the Invention
The present invention relates to a DLL (Delay Lock Loop) circuit, and more particularly to a clock divider and a clock dividing method for a DLL circuit which can reduce a power consumption when a synchronous memory device is kept in a power-down mode that corresponds to a low power consumption state.
2. Description of the Prior Art
As generally known in the art, in a synchronous memory device (hereinafter referred to as a memory device), an internal clock signal is used in order to adjust an operation timing of the memory device and to prevent malfunction of the memory device. In the case that an externally inputted clock is used inside a typical memory device, a time delay occurs. A DLL (Delay Lock Loop) circuit is a circuit which synchronizes a phase of an internal clock of the memory device with a phase of the externally inputted clock in order to control such a time delay.
FIG. 1 is a block diagram of a general DLL circuit.
As illustrated in FIG. 1, the DLL circuit includes a clock buffer unit 100 for receiving an external clock signal, a clock divider 110 for dividing an output signal of the clock buffer unit 100, a delay unit 130 and a delay model 150 for delaying an output signal of the clock divider 110 for a predetermined time, a phase comparator 120 for comparing a phase of an output signal of the delay model 150 with a phase of the output signal of the clock divider 110, and a DLL signal driving unit 140 for receiving output signals of the delay unit 130 and outputting an internal clock signal used in the memory device.
Clock buffers 101 and 102 of the clock buffer unit 100 are buffer circuits that convert a potential level of the externally inputted clock signals CLK and /CLK into a potential level used inside the memory device. Generally, the clock buffers of the memory device are activated by a clock enable signal CKE (not illustrated).
The clock divider 110 receives and divides the output signal Rise_clk of the clock buffer 102. The clock divider 110 divides the frequency of the clock signal Rise_clk into ½M (here, M is the number of dividers), and outputs two output signals S2 and S3. The output signal S2 is an inverted signal of the output signal S3. The output signal S2 of the clock divider 110 is applied to the phase comparator 120 after being delayed for a predetermined time through a third delay line and the delay model 150. For reference, the delay model 150 is a dummy delay unit for compensating for a phase difference between the output signal S3 and an output signal (i.e., feedback signal).
The phase comparator 70 compares the phase of the output signal S3 of the clock divider with the phase of the output signal (i.e., feedback signal) of the delay model 150, and reduces the time difference between the two output signals.
The output signal of the phase comparator 120 is applied to a shift controller of the delay unit. If the phase difference is 0, the shift controller outputs a DLL_lockb signal so that a shift register maintains its present state. On the contrary, if there exists any phase difference, the shift controller controls the shift register to adjust a delay time of the third delay line. An output signal SR of the shift controller makes the shift register shift to the right, and another output signal SL of the shift controller makes the shift register shift to the left. First and second delay lines delay output signals Rise_clk and Fall_clk of the clock buffers 101 and 102 for a predetermined time under the control of the shift controller, and provide corresponding output signals, i.e., an input rising clock irclk and an input falling clock ifclk. The first to third delay lines are composed of a logic circuit having a very short delay time to reduce a jitter.
The first and second DLL signal drivers of the DLL signal driving unit 140 are buffers for providing DLL clock signals used in the memory device. Accordingly, output signals, i.e., a rising clock_dll rclk_dll and a falling clock_dll fclk_dll, of the first and second DLL signal drivers 140 are used as the internal clock signals.
The DLL circuit compensates for the time difference between the externally inputted clock signal CLK and the internal clock signal. Accordingly, the output signals, i.e., the rising clock_dll rclk_dll and the falling clock_dll fclk_dll, of the first and second DLL signal drivers, which are the internal clock signals of the memory device, are synchronized with the external clock CLK through the DLL circuit.
FIG. 2 illustrates a circuit diagram of the clock divider illustrated in FIG. 1.
The clock divider 110 includes first to third dividers 200, 201 and 220, which are connected in series. That is, an output signal of the first divider 200 is applied to an input terminal of the second divider 210, and an output signal of the second divider is applied to an input terminal of the third divider 220. In FIG. 2, the signal S1 corresponds to the signal Rise_clk in FIG. 1, and the signal S2 is an inverted signal of the signal S3.
The first divider outputs a clock signal A, which is obtained by dividing the frequency of the clock input signal S1 into ½. The second divider outputs a clock signal B, which is obtained by dividing the frequency of the output signal A of the first divider into ½. Accordingly, the frequency of the output signal B of the second divider is ¼ of the frequency of the clock input signal S1. The third divider outputs a clock signal C, which is obtained by dividing the frequency of the output signal B of the second divider into ½. Accordingly, the frequency of the output signal C of the third divider is ⅛ of the frequency of the clock input signal S1. This clock divider is called a ⅛-clock divider. As shown in FIG. 3, the duty rates of the output signals of the first to third dividers are not identical, but the duty rates can be modified if needed.
The respective divider circuit of FIG. 2 is composed of NAND gates, but many modifications thereof can be made by those skilled in the art.
FIG. 3 is a timing diagram of the clock divider illustrated in FIG. 2.
As show in FIG. 3, the period of the clock signal S1 applied to the first divider is tCK. The frequency of the output signal A of the first divider is ½ of the frequency of the clock signal S1, and the width of the high-level pulse signal is the same as the period of the clock signal S1. Also, the ⅛-clock divider outputs an output signal S2 of which the width of a low-level pulse signal is tCK. As show in FIG. 3, the output signals S2 and S3 of the conventional clock divider are not controlled by an externally inputted clock enable signal CKE, and thus they are processed irrespective of the state of the memory device. Accordingly, even in the case of a power-down mode in which the power consumption of the memory device is reduced, the output waveform of the clock divider becomes the same as that in a non-power-down mode of the memory device. For this reason, the DLL circuit consumes the same amount of current as that in the non-power-down mode even though the memory device is in the power-down mode.
Generally, in the case that the memory device is in the power-down mode, the power supply of the memory device is stabilized. Thus, it does not cause big problem even if the number of times of phase comparison is reduced in the power-down mode in comparison to that in the non-power-down mode.
As described above, the conventional DLL circuit has the drawbacks that even if the memory device is in the power-down mode, the DLL circuit generates the internal clock signal, which is to be used inside the memory device, in the same manner as in the non-power-down mode, and this causes an unnecessary current consumption.